16. Memory Management

16.2 Virtual Address Space

The processor uses either 32-bit or 64-bit address spaces , depending on the operating and addressing modes set by the Status register. Table 16-1 lists the decoding of these modes.

The processor uses the following addresses:

virtual address VA[43:0]
region bits VA[63:59]

If a region is mapped, virtual addresses are translated in the TLB. Bits VA[58:44] are not translated in the TLB and are sign extensions of bit VA[43].

In both 32-bit and 64-bit address mode, the memory address space is divided into many regions, as shown in Figure 16-3. Each region has specific characteristics and uses. The user can access only the useg region in 32-bit mode, or xuseg in 64-bit mode, as shown in Figure 16-1. The supervisor can access user regions as well as sseg (in 32-bit mode) or xsseg and csseg (in 64-bit mode), shown in Figure 16-2. The kernel can access all regions except those restricted because bits VA[58:44] are not implemented in the TLB, as shown in Figure 16-3.

The R10000 processor follows the R4400 implementation for data references only, ensuring compatibility with the NT kernel. If any of the upper 33 bits are nonzero for an instruction fetch, an Address Error is generated. Refer to Table 16-2 for delineation of the address spaces.

Generated with CERN WebMaker